1. Field of the Invention
The invention relates generally to clock generation in a programmable logic device and more specifically to elimination of abnormally narrow pulses from a dynamically controlled clock.
2. Background of the Invention
This application relates to U.S. application Ser. No. 11/563,632 (the '632 application), titled “Low Power Mode” and filed Nov. 27, 2006, which is incorporated herein by reference. In the '632 application, describes reducing power consumption across a switch, such as an unprogrammed antifuse. The power reduction applies to antifuses, transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches may be uncoupled from signals driving the switches. Next terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
In the '632 application, clocks are disabled (601 in FIG. 6A) and enabled (616 in FIG. 6B) when respectively entering and exiting a sleep mode. When the clocks are dynamically controlled (i.e., disabled and enabled during runtime), a last pulse before being disabled and a first pulse when being re-enabled may be arbitrarily narrow. Such narrow pulses in a conventional system may lead to uncertain clocking of components. Therefore, a need exists to provide a regulated pulse with for a system having a dynamic clock control and a low power mode.